This invention relates to a MOS-type memory circuit constructed of a high-speed static RAM, etc., and more particularly to a MOS-type memory circuit which reduces the delays of word lines thereby to attain a raised operating speed and to realize the widening of a "write" timing margin.
FIG. 1 shows the word lines of a prior-art static RAM and the peripheral circuits thereof. Referring to the figure, symbols 1D-nD denote NAND circuits for decoders, and symbols 1I-nI denote inverters for word line drivers. Symbols 1l-nn indicate memory cells, each of which is configured of two resistance elements and four transistors as illustrated in FIG. 2 by way of example. Further, the static RAM includes word lines 1W-nW and bit lines B1-Bn, B1-Bn. Shown at symbols 1a-na, 1b-nb, and 1c-nc are nodes.
Next, the operation of the static RAM will be described. Each of the decoders 1D-nD is constructed of the NAND circuit, the output of which becomes an "L" (low) level only when all the inputs thereof are at an "H" (high) As a result, only one of the nodes 1a-na becomes the "L" level. Accordingly, only one of the word lines 1W-nW is brought to the "H" level by the inverters 1I-nI. Thus, the data items of all the cells connected to the word lines brought to the "H" level are delivered to the corresponding bit lines B1-Bn. Herein, since the word lines are usually wired of polycrystalline silicon, they have resistances of certain value. Meanwhile, since each of the word lines forms the gates of the access transistors Q5, Q6 of the memory cell M.C. shown in FIG. 2, it has a gate capacitance of certain value. The resistances and the capacitances constitute distributed constant circuits. In consequence, operating waveforms differ greatly between the base ends of the word lines, namely, the ends to which the inverters 1I-nI for the word line drivers are connected, and at the distal ends of the word lines, namely, the ends which are opposite to the base ends, and the nodes 1c-nc on the distal end side undergo great delays with respect to the nodes 1b-nb on the base end side.
Since the prior-art MOS-type memory circuit is constructed as described above, it has been inevitable that each word line operates as a distributed constant circuit having a certain time constant and incurs a delay. The division of the word line has been performed as expedients for solving this problem. With the increase in memory capacity, however, it has been limited in relation to a chip size to suppress the word line delay to an infinitesimal value.